WorkshopS Schedule

DR. NING-CHENG LEE
Principal Consultant, USA

22 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

For electronic devices, solder joints often are the weakest link in terms of reliability. The failure of solder joints may be caused by temperature, stress, electrical current, or chemical reactions, and may occur at level one and level two, depending on the device type and application conditions. In this course, the Part 1 will address the electromigration issue at die attach level for high power devices, and the Part 2 will address the solder joint behavior based on fundamental material properties and the failure modes will be introduced, with emphasis on lead-free solder joints at both level 1 and level 2.

DR. NING-CHENG LEE
Principal Consultant, USA

23 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

The industry is evolving very rapidly, with multiple challenges emerging at the same time on soldering. The cost, the reliability, and the reduced process temperature. Any one failed to address any of those challenges will be left behind in this fierce competitive environment. This course will bring the answer to you, with the most updated information on the new solder materials developed, and will also help you to justify the selection of solder types which fit best for your applications. The course is divided into two parts, with part 1 addressing the cost and reliability, and part 2 address the 5G applications.

DR. NING-CHENG LEE
Principal Consultant, USA

24 July 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

With abundant case studies illustrating the principle and application of Design for Manufacturability (DFM) and Design for Reliability (DFR) in advanced soldering technology, you will be able to apply both on your SMT design and process of soldering job and achieve high yield and high reliability very easily, and also be ready to face the new challenges emerged. This course covers the principles of DFX, aiming at allowing the course taker maximize the output of manufacturing yield and reliability when addressing advanced soldering technology. The content contains two Parts, Part 1 emphasizes on Design for Manufacturability (DFM) and Part 2 emphasizes on Design for Reliability (DFR) for SMT manufacturing. Each of the design consideration is exemplified with a real case study, with fundamental consideration and mechanisms of challenges well illustrated.

DR. TOM DORY
Principal Consultant, USA

22 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Workshop participants will receive a detailed review of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.

DR. TOM DORY
Principal Consultant, USA

23 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

This workshop provides details on current and future assembly processes and technologies used in fan out package assembly. Examples taken from mobile smart phones to advanced server computing will be presented. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes. The package end user, designer and sub-cons must compare all package options on the basis of functional attributes including form factor, I/O density, performance & cost to select appropriate package from the many fan out options available. Currently there are several choices for package assembly using fan out wafer level packages (FOWLPs). The original fan-out package; the embedded wafer-level ball-grid array (eWLB) continues to be popular. At the low cost end are low density fan out packages with <500 IOs with >8 micron L/S. At the high cost end are stacked die packages with >500 IOs and < 8 micron L/S. Multiple die can now be included in a fan out package incorporating stacked die connected using Through Silicon Vias (TSVs). The use of 200 or 300mm reconstituted wafer carrier to a panel as the assembly vehicle will be discussed. The workshop begins with a detailed comparison of advanced packaging technologies including all varieties of fan out packages including FOWLPs & SiPs to 3D stacked dice interconnected with TSVs. The workshop will discuss a chip first and chip last assembly option for fan out packages. Both wire bond and flip chip options will be compared. Types of fan out packaging include Wafer Level Fan Out, Panel Level Fan Out with embedded die, and Chip Last Fan Out packaging. These package options with low cost materials and process flows create simple low density devices.

DR. TOM DORY
Principal Consultant, USA

24 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

This one-day workshop provides a complete overview of current HVM wirebonding assembly process options and metrology specific challenges. A small bond pad pitch is critical as the number of bond pads that must be placed per unit area increases. This will require a large leap in wire manufacturing capability and improved wire bonding tools. New challenging assembly processes including direct wirebonding to Cu pads on ULK materials will be covered. Different methods of wire bonding such as thermosonic, ultrasonic and thermocompression will be discussed in this workshop. Several options for Cu wire are presented in the workshop. Using easy to understand terminology an in-depth review of wire bonding processes in assembly manufacturing and first level interconnects are discussed. Package and assembly technologies, wire bonding quality such as the wire pull test and a non-destructive pull test are covered. Wire bonding for COB applications, stacked die packages, coreless organic substrates will be discussed. Wire bonding problems using Au, Al or Cu wire and tape automated bonding are part of the class. Wire bonding infrastructure is so extensive that no other chip-interconnection technology can completely displace wire bonding in the foreseeable future.

DR. BHANU SOOD
Commodity Risk Assessment Engineer, Reliability and Risk Assessment Branch, NASA Goddard Space Flight Centre, USA

22 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and more sophisticated tools, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes, and loss of resources and customers due to recurrence of failures. The tools and techniques applied by many test and FA labs today are geared only towards uncovering the apparent causes of failure, not necessarily the root causes. Thus, the corrective actions applied by manufacturers or end-users do not always eliminate problems. This can result in expensive, time-consuming, repeat occurrences of failures. This one-day workshop will discuss a range of topics, including root cause analysis, physics-of-failure principles, and failure mechanisms in electronics. Specimen preparation techniques, non-destructive and destructive analysis, and materials characterization will also be discussed. The first day of the workshop will present methodologies for identifying potential failure mechanisms in electronics based on the failure history and, systematic approaches to root cause analysis. The second day will cover failure analysis techniques geared towards various failure mechanisms, along with numerous component and PCB assembly failure analysis case studies that illustrate the techniques and analysis. Failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies.

DR. BHANU SOOD
Commodity Risk Assessment Engineer, Reliability and Risk Assessment Branch, NASA Goddard Space Flight Centre, USA

23 & 24 August 2022 (0900 – 1500) – GMT +8

WORKSHOP OVERVIEW

Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependent. This two-day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the eld conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues.

 
BOB WILLIS
Principal Consultant, England

22  August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

To achieve the sought-after electronics miniaturization and the ever-increased circuit density and functionality, two families of IC packages, Bottom Termination Component (BTC) and Package-on-Package (PoP), are among the commonly adopted IC packages.This workshop focuses on BTCs and PoPs in packaging and the downstream manufacturing in assembly.

With the objective to optimize the production yield and product reliability, this workshop will provide an overview of BTC and PoP technologies and applications, as well as address the important aspects of materials, techniques, processes and reliability for both Pb-free and SnPb products. Various configurations of BTCs (e.g. QFN, LGA, MLF, SON, DFN) in periphery-leaded and solder-ball array packages will be outlined. The best practices of assembling BTCs including solder material, PCB assembly processes and rework will be discussed. The workshop will also deal with the real-world production issues and discuss the BTC solder joint reliability, and what it takes to make reliable solder interconnections in both package and PCB/module levels. The parallelism and distinctions between PoPs and BGAs, in particular – co-planarity, thermal stability of molding materials and conformal coating, will be outlined. The options and best practices of assembling PoPs including solder material, PCB assembly processes and rework will be outlined. The real-world production issues related to PoP solder joint reliability for upper package and lower package, and what it takes to make reliable solder joints will be discussed. Attendees are encouraged to bring their issues for discussion.

BOB WILLIS
Principal Consultant, England

23 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Join us for a practical look at the advantages and use of Low Temperature Soldering (LTS) in this special workshop. LTS is gaining significant interest in the industry to reduce cost, prevent component and PCB damage and improve reliability. It’s different but that does not mean it cannot be introduced into your process with existing process equipment. Generally speaking, solders used regally in assembly reflow at over 230oC, low temperature solders reflow at under 180oC. Many companies have been using tin/bismuth alloys for some years reducing cost on PCBs and energy. Other companies have been using tin/indium for rework of lead-free area array packages with success. There are savings to be made even if the cost of some solder alloy is more expensive provided you consider the total cost of manufacture. We produced the first book, video and interactive guide on Pin In Hole Intrusive Reflow, so we believe we are in a good position to help engineers achieve high yields with low temperature materials with standard assembly or PIHR.

PROF. AMLAN CHAKRABARTI
Professor & Director, A.K Choudhury School of Information Technology, University of
Calcutta, India

22 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Distributing power in high speed, high complexity integrated circuits has become a challenging task as power levels exceeding tens of watts have become commonplace while the power supply is plunging toward one volt. This workshop is dedicated to this important subject. The primary purpose of this workshop is to provide insight andintuition into the behavior and design of power distribution systems for high speed, high complexity integrated circuits.

PROF. AMLAN CHAKRABARTI
Professor & Director, A.K Choudhury School of Information Technology, University of Calcutta, India

23 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Modern embedded computer systems perform complex data processing jobs and hence often requires a large set of processors (homogeneous or heterogeneous) for higher performance. To support the various application needs the embedded system platform integrates various types of processing elements into the system, including general-purpose CPUs, application-specific instruction-set processors (ASIPs), digital signal processors (DSPs), as well as dedicated hardware accelerators implemented as application-specific integrated circuits (ASICs) and intellectual property (IP) components. This converges to the idea of System-On-Chip (SoC) design and more commonly Multi-processor System on Chip Design (MPSoC). However, the large size and complexity of these systems poses a great challenge to design and validation using traditional design flows. System designers are forced to move to higher levels of abstraction to cope with the many problems, including large number of heterogeneous components, complex interconnect, sophisticated functionality. This workshop will present the key techniques and challenges in regards to the efficient design of SoC/MPSoC based Embedded Systems with some important case studies.

PROF. AMLAN CHAKRABARTI
Professor & Director, A.K Choudhury School of Information Technology, University of Calcutta, India

24 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Distributing power in high speed, high complexity integrated circuits has become a challenging task as power levels exceeding tens of watts have become commonplace while the power supply is plunging toward one volt. This workshop is dedicated to this important subject. The primary purpose of this workshop is to provide insight andintuition into the behavior and design of power distribution systems for high speed, high complexity integrated circuits.

PHIL ZARROW
President & Principal Consultant, ITM Consulting, USA

22 & 23 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

The SMT Electronics Assembly Class is a practical overview of the many different processes and materials used in through-hole and surface mount technologies (SMT). It is a focused two-day long workshop, which provides students with the opportunity to learn and understand the processes, equipment, and materials used in today’s manufacture of electronic assemblies. It is taught by an experienced and knowledgeable instructor who has worked in a variety of electronics manufacturing related fields. Combining lecture, videos and discussion, this Electronic Assembly Basic Training workshop was designed to give a very comprehensive and complete ‘immersion’ into SMT and mixed technology PCB assembly. People who are new to the field as well as somewhat experienced personnel who want to “fill in the gaps” have found this workshop to be a perfect solution. As it runs only two days, it is extensive (and non- superfluous) without taking people ‘out of the shop’ for an extended period of time: learn, absorb and take that knowledge back to the manufacturing floor.

PHIL ZARROW
President & Principal Consultant, ITM Consulting, USA

24 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Phil Zarrow of ITM Consulting will present a journey through troubleshooting the most common defects in SMT with an emphasis on identifying the fundamental root causes, and an entertaining overview of best practices. This is based upon real-world problems encountered in troubleshooting process, equipment and materials problems throughout the electronics assembly industry all over the world. Case studies are used throughout the workshop.

SHURAS VASU
 Principal Consultant, Malaysia

23 & 24 August 2022 (0900 – 1700) – GMT +8

WORKSHOP OVERVIEW

Internal audit is fundamental to all management system standards as it is a means to establish status of conformity. However, with the latest update on the management system standards based on Annex SL, the emphasis has shifted to risk and performance. With this shift, an auditor has to change its perception of an audit – understand not only how to audit a system based on the requirements of the standard but also at the same time understand how an organization addresses its risks and opportunities to achieve its expected performance. Results of internal audits provide particularly useful information to management to continually improve its management system. The quality of the results depends mainly on the competency of the auditors. This course provides delegates with an understanding of how to conduct an audit on management system based on ISO 9001:2015 focusing on the organization’s processes, risk approach and its customer satisfaction performance.
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