For electronic devices, solder joints often are the weakest link in terms of reliability. The failure of solder joints may be caused by temperature, stress, electrical current, or chemical reactions, and may occur at level one and level two, depending on the device type and application conditions. In this course, the Part 1 will address the electromigration issue at die attach level for high power devices, and the Part 2 will address the solder joint behavior based on fundamental material properties and the failure modes will be introduced, with emphasis on lead-free solder joints.
In this workshop the detailed review of failure analysis methods and reliability testing in assembly will be discussed. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A through understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of engineers from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.
Root Cause Analysis (RCA) & effective corrective actions is a popular and often-used technique that helps people answer the question of why the problem occurred in the first place and how prevention can be done to prevent recurrence. It seeks to identify the origin of a problem using a specific set of steps, with associated tools, to find the primary cause of the problem, so that you will be able to determine what happened, determine why it happened and figure out what to do to reduce/prevent the likelihood that it will happen again. The Root Cause Analysis & Systematic Problem Solving Process involves 6 stages/steps and linked to Define the Problem, Collect Data, Identify Possible Causal Factors, Identify the Root Cause(s) Recommend and Implement Solutions and Verifying the effectiveness of the solutions.
The SMT Electronics Assembly Class is a practical overview of the many different processes and materials used in through-hole and surface mount technologies (SMT). It is a focused two-day long workshop, which provides attendees with the opportunity to learn and understand the processes, equipment, and materials used in today’s manufacture of electronic assemblies. Combining lecture, videos and discussion, this Electronic Assembly Basic Training workshop was designed to give a very comprehensive and complete ‘immersion’ into SMT and mixed technology PCB assembly. As it runs only two days, it is extensive (and non- superfluous) without taking people ‘out of the shop’ for an extended period of time: learn, absorb and take that knowledge back to the manufacturing floor.
Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions which is; a) it provides the necessary mechanical support for the components in the circuit; b) it provides the necessary electrical interconnections, and c) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues.
The industry is evolving very rapidly, with multiple challenges emerging at the same time on soldering. The cost, the reliability, and the reduced process temperature. Any one failed to address any of those challenges will be left behind in this fierce competitive environment. This course will bring the answer to you, with the most updated information on the new solder materials developed, and will also help you to justify the selection of solder types which fit best for your applications. The course is divided into two parts, with part 1 addressing the cost and reliability, and part 2 address the low temperature soldering.
Participants in this workshop will receive a complete overview of current high volume manufacturing, HVM, wire bonding assembly process options and metrology challenges. Miniaturization of wire bonding is critical as the number of bond pads that must be placed per unit area increases. This requires a large leap in wire manufacturing capability and improved wire bonding tools. New challenging assembly processes including direct wirebonding to Cu pads on ULK materials will be discussed. Different methods of wire bonding such as thermosonic, ultrasonic and thermocompression will be covered in this workshop. Several options for Cu wire use are presented in the workshop. Using easy to understand terminology an in-depth review of wire bonding processes in assembly manufacturing and first level interconnects are presented. Package and assembly technologies, wire bonding quality including wire pull and sheer test are discussed in detail. Wire bonding for chip on board, COB, applications, organic substrates, wire bonding problems using Au, Al or Cu wire and tape automated bonding are part of the class. Wire bonding infrastructure is so extensive that no other chip-interconnection technology can completely displace wire bonding in the foreseeable future.
The journey through troubleshooting the most common defects in SMT with an emphasis on identifying the fundamental root causes, and an entertaining overview of best practices will be discussed in this workshop. This is based upon real-world problems encountered in troubleshooting process, equipment and materials problems throughout the electronics assembly industry all over the world. Case studies will be used throughout the workshop.
Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and more sophisticated tools, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes, and loss of resources and customers due to recurrence of failures. The tools and techniques applied by many test and FA labs today are geared only towards uncovering the apparent causes of failure, not necessarily the root causes. Thus, the corrective actions applied by manufacturers or end-users do not always eliminate problems. This can result in expensive, time-consuming, repeat occurrences of failures. This two day workshop will discuss a range of topics, including root cause analysis, physics-of-failure principles and failure mechanisms in electronics. Specimen preparation techniques, non-destructive and destructive analysis, and materials characterization will also be discussed. The first day of the workshop will present methodologies for identifying potential failure mechanisms in electronics based on the failure history and, systematic approaches to root cause analysis. The second day will cover failure analysis techniques geared towards various failure mechanisms, along with numerous component and PCB assembly failure analysis case studies that illustrate the techniques and analysis. Failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies.
With abundant case studies illustrating the principle and application of Design for Manufacturability (DFM) and Design for Reliability (DFR) in advanced soldering technology, you will be able to apply both on your SMT design and process of soldering job and achieve high yield and high reliability very easily, and also be ready to face the new challenges emerged.
Flip chip packaging is not new but new technology requires more connections between the die and package, a tighter bump pitch and more functionally in the package. Tablets and smart phones all use flip chip packaging with thinned die and thin packages. All technology drivers bring new issues that must be addressed. These issues include new copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Wafer thinning processes and some stacked die package options will be reviewed. This workshop will begin with a discussion of current flip chip assembly. We will then discuss the new technology options and issues. The objective of this workshop is to provide an improved understanding of current flip chip package options and assembly flows. The newer HVM package material and design options are discussed. Wafer thinning and handling including bonding and debonding methods will be covered. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.
Managing shop floor can be a disaster for many organisations. Lack in the skill of the people, poor communication, bad tracking of the performance, lack of best practices , poor motivation and others are common thing that we see in an under performing organisation. As the world’s business climate changes, it is getting more difficult for us to remain competitive. Customers demand changes, technological changes, and competitive forces change. In other word, our environment has become very turbulent. With the poor shop floor management added , the organisation remain noncompetitive and further become unprofitable organisation. The New Shop Floor Management will address the importance of shop floor management, providing ideas, techniques, concepts and philosophy necessary to practice better shop floor management, illustrating how these are applied in different companies, encouraging participants to take significant steps towards continuous improvement that involve everybody, upgrading skills and deepening the insights for self management to maximize everybody’s’ potential .In short rather than viewing the shop floor only from the top down, this session attempts to address the organisations needs from shop floor up, presenting a new perspective of the shop floor and its’ linkage to the total organisation.
Part 1: Background (1.5hrs)
1.1. Relevance of Moore’s Law in Present Computing Systems
1.2. Modern Hardware Designing in ASIC and FPGAs
1.3. Design of Embedded System and System on Chips (SoCs)
1.3.1. IP based SoC Life Cycle
1.3.2. SoC Design Flow
1.3.3. SoC Verification Flow
1.3.4. SoC Test Flow
1.4. Security vs Test/Debug
1.5. Importance of Hardware Security
Part 2: Attacks: Analysis, Examples and Threat Models (2.5hrs)
2.1. Hardware Trojans
2.1.1. Structure and Modeling
2.1.2. Taxonomy
2.1.3. Benchmarks
2.2. Counterfeiting/ Electronic Supply Chain Vulnerability
2.2.1. Steps of Electronic Supply Chain (Design/Fabrication/Assembly/Distribution/Lifetime/End of Life)
2.2.2. Supply Chain Issues
2.2.3. Security Concerns
2.2.4. Trust Issues
2.3. IP Piracy and Reverse Engineering
2.3.1. What are Hardware IPs? (Hard IPs and Soft IPs)
2.3.2. Related Security Issues
2.3.2.1. Overproduction
2.3.2.2. IP Piracy
2.3.2.3. Reverse Engineering
2.4. Side Channel Attacks
2.4.1. Timing based Side Channel Attacks
2.4.2. Power based Side Channel Attacks
2.4.3. Electromagnetic based Side Channel Attacks
2.4.4. Fault Injection Attacks
2.4.5. Covert Channels
Part 3: Countermeasures (2hrs)
3.1. Test Time Detection Strategies
3.1.1. Logic Testing
3.1.2. Side Channel Analysis
3.1.3. Physical Testing
3.2. Authentication based Strategies
3.2.1. Physical Unclonable Functions (PUFs)
3.2.2. Proof Carrying Codes (PCCs)
3.2.3. Watermarking
3.3. Obfuscation Strategies
3.4. Runtime Mitigation Mechanisms
3.4.1. Redundancy based Techniques
3.4.2. Self Aware Techniques
Part 4: Simulation Models (2hrs)
4.1. General Designing on FPGAs and ASICs
4.2. Generating Attacks on Designs implemented in FPGA and ASIC Platforms
4.3. Securing the Designs
Part 1: Background (1.5 hrs.)
a) On-Chip Power Distribution Network.
b) Decoupling Capacitance.
c) Power-grid modelling and voltage-drop analysis.
d) Impact of supply noise on circuit performance.
e) Active supply-voltage regulation and supply-noise measurement.
Part 2: Vector-less Analysis Of Supply-Noise Induced Delay Variation (2.5 hrs.)
a) Delay model for supply fluctuations.
b) Voltage-drop sensitivity computation.
c) Block-current constraints.
d) Overall path-based delay-maximization formulation.
e) Block-based circuit-delay model.
Part 3: Power-Supply-Drop Analysis (1.0 hrs)
a) Constraint-based early supply-drop analysis.
b) Statistical supply-drop analysis.
c) Global-optimization approaches.
Part 4: Inductance, Locality And Resonance In Power Supply Networks (1.5 hrs)
a) Full-wave on-die inductive effects.
b) Mid-size model and capacitive effects.
c) Complete package-die model.
d) CAD implications.
Part 5: Digital Circuit-Techniques For Active Inductive-Supply-Noise Suppression (1.5 hrs.)
a) Charge-injection-based active decoupling circuit.
b) High-voltage charge-pump-based active decoupling circuit.
c) High-voltage shunt-supply-based active decoupling circuit.
d) Digital on-chip oscilloscope for supply-noise measurement.
Part 1: Background (1 hrs.)
1.1 Radiation Sources
1.2 Radiation Interactions
a) Energy loss through collision (heavy particles).
b) Energy loss of electrons and positrons.
c) Bremsstrahlung.
d) Cherenkov and Transition radiation.
e) Photo effect.
f) Compton scattering and pair production.
Part 2: Effect of radiation on solid state devices (2hrs.)
a) Lattice displacement.
b) Ionization effects.
c) Resultant effects.
d) Total ionizing dose effects.
e) Transient dose effects.
Part 3: Various fault models (1.5 hrs)
a) Stuck at fault.
b) Soft error.
c) Transient error.
d) Permanent error.
Part 4: Performance of various commercially available computing devices like in presence of radiation (1.5 hrs)
a) Audrino and Rasberi pi as IoT node.
b) FPGA and Reconfigurable devices.
c) ASICs.
Part 5: Various kinds of error mitigation methods (1 hrs.)
a) TMR.
b) CED.
c) Various error correcting and detecting code.
Part 6: Basic fabrication methodology for development of radiation hardened devices (1hrs.)
a) Development of Radiation Hardened Deceives.
b) Various kind of shielding.
