The EPCON ASIA 2018 is a workshop series and conference that is highly anticipated , attended by profesionals from the semiconductor and electronics manufacturing sector. This convention blends together a strategic outlooking high tech manufacturing and technical trainings covering process optimisation, quality control and inspection. This is the perfect platform to garner innovative and practical solutions, connect with your peers and derive business opportunity.
Breaking New frontiers in electronic manufacturing
The 16th National Electronics Packaging Conference kicked off with a forum and dinner hosted by Knowledge Group of Companies at Equatorial Hotel on June 5.
In his Opening Speech, Finance Minister Lim Guan Eng stated that worldwide sales of semiconductors from the first quarter of 2017 amounted to US$92.6 billion, up by 18.1 percent compared to the corresponding period of 2016.
As Penang provides 8 percent of the worldwide sales , this has made manufacturing generally a booming sector globally with this significant progress in the E&E sector. There's a need to create a valuable pipeline of talent to embrace new technologues that is rapidly changing.
YB TUAN LIM GUAN ENG
Opening for NEPCON 2017 Workshop Series
Director, Digital Manufacturing & Industrialization., Osram Opto Semiconductors
The use of Conformal coating has provided benefits to industry for many years either in the high reliability market sector or where products have to deal with extreme environmental conditions or simply in use in consumer applications. Coatings are widely used in many different industries like telecommunications, automotive and consumer products have benefited from the use of selective coating but for different reasons. This workshop will provide guidance to the use of coatings, their application and process, product benefits, inspection and quality control. There are many new challenges with the coating and the environment which has highlighted failure of corrosion and tin whisker growth. This session will show you how to prevent these problems and how to test your products.
Electronics assembly with lead-free solder has been mainstream now of 12 years. This change form tin-lead solder has brought numerous challenges: which lead-free solder to use, resolving new defects such as the head-in-pillow (HIP) defect and voiding, backward and forward compatibility with tin-lead solder, tin whiskers, reliability concerns and others. This workshop will discuss these issues and approaches to resolve them in detail. This workshop will help the attendee to develop strategies to achieve high yields and reliability in electronic assembly.
This fast paced workshop will discuss a range of topics, including root cause analysis, physics-of-failure principles and failure mechanisms in electronics. Specimen preparation techniques, non-destructive and destructive analysis, and materials characterization will also be discussed. The first half of the workshop will present methodologies for identifying potential failure mechanisms in electronics based on the failure history and, systematic approaches to root cause analysis. The latter half will cover failure analysis techniques geared towards various failure mechanisms, along with numerous failure analysis case studies that illustrate the techniques and analysis. Failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies.
We don’t assemble electronics in “perfect world”. Defects happen! This workshop examines Failure and Root Cause analysis of PCBA defects. Detection and determination methodologies and procedures will be discussed. Cause and effect of defects relative to specific processes and equipment centers as well as materials are presented. Key causes of assembly problems and low yields are identified and resolved.
Most of the industry worldwide have been running no clean processes for many years and have often, understandably, neglected important issues like design for cleaning, selecting compatible components and compatibility between cleaning materials and flux residues. With increased miniaturisation and the demands of modern circuits boards cleaning has come back into fashion due to process and product failures. Conformal coating is another process which has demanded special levels of surface cleanliness to guarantee coating adhesion and long term reliability. Although there are high reliability produces in many market sectors that use coating with no clean others may want that extra confidence of removing unknow residues. Most of the industry worldwide have been running no clean processes for many years and have often, understandably, neglected important issues like design for cleaning, selecting compatible components and compatibility between cleaning materials and flux residues. With increased miniaturisation and the demands of modern circuits boards cleaning has come back into fashion due to process and product failures. Conformal coating is another process which has demanded special levels of surface cleanliness to guarantee coating adhesion and long term reliability. Large companies have the ability to test and evaluate all materials that go into an electronic assembly and test the reliability of the product under different environmental conditions, smaller companies do not. This workshop features many unique process video clips on testing and failures and make his sessions come alive.
This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues.
The printed circuit board is the building block of any electronic assembly and as such must exceed specification and be totally compatible with the assembly processes used in modern assembly. Failures in PCB fabrication can be cosmetic, often the most common reason for rejection in manufacture or assembly. Failures can be found during assembly and final test which are not ideal but much better than field returns. A common fault is no or incorrect specification of the bare board in design or via purchasing. This can lead to failures in manufacture. During this workshop, trainer will highlight test methods you can try and tricks of the trade to understand how PCBs can fail and how to eliminate many of the common causes. After the workshop there is a Q&A session which provides ample time for all delegate questions to be answered.
Quickly finding and eliminating package defects and failures due to assembly issues is critical to the IC business. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of people in many disciplines is needed in order to achieve high yield and reliability. Each needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods. The workshop participants will learn about failure analysis methods and reliability.
The objective of this workshop is to provide an improved understanding of current flip chip package options and assembly flows. The newer HVM package material and design options are discussed. Wafer thinning and handling including bonding and debonding methods will be covered. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.
This workshop provides details on current and future assembly processes and technologies used in fan out package assembly. Examples taken from mobile smart phones to advanced server computing will be presented. The workshop continues with packaging assembly flows for each major package type. Details on copper pillar flip chip interconnect structures, process flows and materials will be discussed. Copper pillar flip chip attachment methods including thermal reflow, thermo-compression bonding and the use of non-conductive paste will be reviewed. The objective of this workshop is to provide the delegates with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes.
Statistical Process Control (SPC) is vital for monitoring and controlling electronic assembly processes, especially stencil printing. This workshop will cover the basics of SPC for stencil printing and teach the student how to establish an SPC program for stencil printing or other SMT process at their facility.
Stencil Printing causes about two thirds of end of the line defects. Hence, establishing an SPC Stencil Printing program for electronic assembly will increases first pass yields and improve product reliability.
Design of Experiments (DOE) is an off-line quality improvement methodology that dramatically improves industrial products and processes thus enhancing productivity and reducing costs. Input factors are varied in a planned manner to efciently optimize output responses of interest with minimal variability. This course will provide delegates with basic DOE knowledge & techniques that have been specically designed to deal with common process optimization problems that encountered by engineers in industry. These techniques will be demonstrated by using Minitab software with actual industrial data.
Design of Experiments (DOE) is an off-line quality improvement methodology that dramatically improves industrial products and processes thus enhancing productivity and reducing costs. Input factors are varied in a planned manner to efciently optimize output responses of interest with minimal variability