CONFORMAL COATING APPLICATIONS, INSPECTION,
REWORK & QUALITY CONTROL


7th August 2018


BOB WILLS

President & Principal Consultant
Bobwillisonline.com England


WORKSHOP OVERVIEW

The use of Conformal coating has provided benefits to industry for many years either in the high reliability market sector or where products have to deal with extreme environmental conditions or simply in use in consumer applications. Coatings are widely used in many different industries like telecommunications, automotive and consumer products have benefited from the use of selective coating but for different reasons.

This workshop will provide guidance to the use of coatings, their application and process, product benefits, inspection and quality control. There are many new challenges with the coating and the environment which has highlighted failure of corrosion and tin whisker growth. This session will show you how to prevent these problems and how to test your products. With reference to IPC standards on conformal coating and inspection of coated boards will help a better understanding on what is acceptable to customers.


Each delegate will also receive a FREE set of colour Conformal Coating Inspection & Defect Wall Charts covering coating application and common defects to use on their manufacturing shop floor as a training or inspection aid.


WORKSHOP OUTLINE
  • Why Conformal Coat
  • Clean or No CLean
  • Coating Material Options
  • Coating Process Options
  • Cost of coating assemblies
  • SIR and cleanliness testing
  • Cleanliness testing methods
  • Reliability of Coating
  • Testing & Evaluation of Coatings
  • Correct design for coating
  • Masking options and methods
  • Inspection & Quality Control of Coating
  • In-house or Contracting Services
  • Inspection of coatings & methods
  • Rework & repair of board assemblies
WHO SHOULD ATTEND

This workshop is designed for design, process and quality engineers responsible for introducing coating materials, inspection or auditing suppliers. The workshop is extremely visual and practical making it ideal for manufacturing staff, like all the instructors workshops it not just theory, it’s a “How to Do It Session”.

If a delegate has a process example they would like cover in the workshop it will need to be provided in advance of the session with photographs by email to the presenter.

ISSUES TO BE RESOLVED FOR SMT ASSEMBLY


7th & 8th August 2018


RONALD C. LASKY, PHD, PE, LSSMBB

Instructional Professor, Thayer School of Engineering,
Dartmouth College


WORKSHOP REVIEW

Electronics assembly with lead-free solder has been mainstream now of 12 years. This change form tin-lead solder has brought numerous challenges: which lead-free solder to use, resolving new defects such as the head-in-pillow (HIP) defect and voiding, backward and forward compatibility with tin-lead solder, tin whiskers, reliability concerns and others. This workshop will discuss these issues and approaches to resolve them in detail. This workshop will help the attendee to develop strategies to achieve high yields and reliability in electronic assembly.


WORKSHOP OUTLINE
  • Status of Lead-Free to 2018
    • >Alloy Selections
    •    -Convergence to SAC305
    • > Process Issues
    • > Reiability
    • > Has Lead-Free Implementation had Major
  • “New” Defects and their Amelioration
    • > Grapings
    • > The Head-in-Pillow (HIP) Defect
    •    -Voiding
    • > Fragility
    • >Pad Cratering
  • Mixed Alloys
    • > Backward and Forward Reliability
    • > Process Optimization
  • Alternative Lead-Free Solder Alloys
    • > Low Silver Alloys
    • > The Affect of Dopants
    • > Low Melting Temperature Alloys
    • > Improved Drop Shock and Thermal Reliability Issues
  • Halogen Free Solder Pastes
    • > Why Halogen Free
    • > The Challenges of Determining if a Material is Halogen Free
    • > Implementing a Halogen Free Solder Paste
  • Evaluating a New Solder Paste
    • > Ask around
    • > Check the Website
    • > The 12 Board Solder Paste Evaluator
    • > The Concern for Sheer Thinning
  • Tin Whiskers: A Lingering Threat?
    • > Formation
    • > Factors that Affect TW growth
    • > How Serious is the Threat?
      •    -Convergence to SAC305
    • > Mitigation Techniques
    • > Does Coating Work?
  • Tin Pest: An Unrecognized Threat
    • > What is Tin Pest?
    • > How Does it Form?
    • > What is the Risk?
    • > Tin Pest Minimization
  • Reliability in Depth
    • > The Current Reliability Needs
    • > The Tests
      •    - Thermal
      •    - Fragility
      •    - Vibration
      •    - Creep
    • > Intermetallics
      •    - How they form
      •    - Time and Temperature Kinetics
      •    - Are they brittle?
      •    - Their effect on Reliability
    • > Weibull Analysis of Data
      •    - Weibull Basics
      •    - The Curse of the Early First Fail
      •    - Multiple Failure Modes
WHO SHOULD ATTEND

Any one who cares about achieving high yield and high reliability lead-free solder joints and like to know how to achieve them should take this course

FAILURE ANALYSIS FOR IMPROVED RELIABILITY


8th & 9th August 2018


BHANU SOOD

Reliability and Risk Assessment Branch
NASA Goddard Space Flight Center, USA


WORKSHOP OVERVIEW

Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and more sophisticated tools, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes, and loss of resources and customers due to recurrence of failures. The tools and techniques applied by many test and FA labs today are geared only towards uncovering the apparent causes of failure, not necessarily the root causes. Thus, the corrective actions applied by manufacturers or end-users do not always eliminate problems. This can result in expensive, time-consuming, repeat occurrences of failures.

Root cause failure analysis employs a sequence of non-destructive and destructive analytical techniques to characterize the modes by which failure is manifested, the sites where failure is localized, the fundamental mechanical, electrical, chemical, electrochemical or radiological mechanisms by which failure has occurred, and the factors which precipitated the activation of those mechanisms. Unfortunately, failure analysis is often performed incorrectly or incompletely, leading to a poor understanding of failure mechanisms and causes, and loss of money, customers, and possibly lives due to recurrence of failures.

This fast paced workshop will discuss a range of topics, including root cause analysis, physics-of-failure principles and failure mechanisms in electronics. Specimen preparation techniques, non-destructive and destructive analysis, and materials characterization will also be discussed. The first half of the workshop will present methodologies for identifying potential failure mechanisms in electronics based on the failure history and, systematic approaches to root cause analysis. The latter half will cover failure analysis techniques geared towards various failure mechanisms, along with numerous failure analysis case studies that illustrate the techniques and analysis. Failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies.


WORKSHOP OUTLINE
  • Introduction to reliability
  • Root cause analysis, failure definations, classification of failures
  • Root cause analysis process
  • Tools for hypothezing root cause FMMAEA, fishbone, Pareto)
  • Overview failure cause in electronic devices
  • General approachesused for failure anaysis
  • Overview of failure mechanism in electronics (PCBA level, component level)
    • >ESD/EOS included IC failure modes and sites
    • >Board level failures
    • >Assembly levelfailures
    • >Electrochemical migration, contaminants
    • >Plated through hole (PTH) failures
    • > Failure mechanism due to handling
    • >Interminttent failures, examples of cannot-duplicate, no-fault-found
  • Failure analysis techniques – Non-destructive analysis techniques
    • > X-ray inspection
    • - X-ray Fluorescence (XRF)
    • - Optical microscopy and inspection
    • - Scanning Acoustic Microscopy (SAM)
    • - Electrical Testing
    • - Others
  • Failure analysis techniques – Destructive analysis
    • - DPA, chemical decap, manual decap, laser decap, copper wirebonds
    • - Wire pull, ball bond shear, cold bump pull tests
    • - Fault isolation
    • - Dye-and-pry
    • - Scanning Electron Microscopy and Energy Dispersive Spectroscopy
    • - Metallographic sample preparation, cross-sections
  • Summary of failure analysis process, reporting
WHO SHOULD ATTEND

Reliability Engineers, Failure Analysis Engineers, Engineering Managers, Design Engineers, Component Engineers, Quality Assurance functions and, personnel involved with reliability activities with the Organization

DEFECT ANALYSIS AND PROCESS TROUBLESHOOTING


9th August 2018


PHIL ZARROW

President & Principal Consultant
ITM Consulting, USA


WORKSHOP OVERVIEW

We don’t assemble electronics in “perfect world”. Defects happen! This course examines Failure and Root Cause analysis of PCBA defects. Detection and determination methodologies and procedures will be discussed. Cause and effect of defects relative to specific processes and equipment centers as well as materials are presented. Key causes of assembly problems and low yields are identified and resolved. This seminar is intended for anyone involved in directing, developing, managing and/or executing Failure and Root Cause analysis and defect resolution including managers, engineers and others in manufacturing, quality and design.


WORKSHOP OUTLINE
  • Introduction
    • > Prevention: Process Development and Validation
    • > Variation (Common Cause)
    • > Continuous Improvement
  • Defect Definition
    • > Failure – PCBA does not function
    • > Repair or Scrap
    • > Escapes – Identified by customer
    • > Reduced Reliability
    • > Process Indicator
    • > Special Cause vs. Common Cause
    • > Defect Identification
    • > Inspection (Manual, AOI, X-Ray)
    • > Test (ICT, Functional, Contamination)
    • > False Calls / Escapes
  • Root Cause Analysis
    • > “5 Whys”
    • > Cause and Effect Diagram
    • > 6 M’s
    • > Levels: Specific Processes vs Interactions
  • Process Relationships
    • > Incoming Materials
    • > Handling
    • > Process Problems
    • > Wrong Process
    • > Degraded Process
    • > Poor Process (common cause defects)
WHO SHOULD ATTEND

This course is intended for Manufacturing, Process, Design, Test and Quality Engineering personnel as well as Management who are involved in the production of surface mount or mixed technology assemblies.

CLEANING PRINTED CIRCUIT ASSEMBLIES, DESIGN & PROCESS CONTROL


8th August 2018

BOB WILLIS

President & Principal Consultant
Bobwillisonline.com, England


WORKSHOP OVERVIEW

Most of the industry worldwide have been running no clean processes for many years and have often, understandably, neglected important issues like design for cleaning, selecting compatible components and compatibility between cleaning materials and flux residues. With increased miniaturisation and the demands of modern circuits boards cleaning has come back into fashion due to process and product failures. Conformal coating is another process which has demanded special levels of surface cleanliness to guarantee coating adhesion and long term reliability. Although there are high reliability produces in many market sectors that use coating with no clean others may want that extra confidence of removing unknow residues.

Large companies have the ability to test and evaluate all materials that go into an electronic assembly and test the reliability of the product under different environmental conditions, smaller companies do not. Bob’s workshop features many unique process video clips on testing and failures and make his sessions come alive.

Each delegate on the workshop in addition to a printed copy of the presentation will receive a FREE set of Cleaning Inspection and Quality Control Wall Charts which also cover defects seen during assembly.


WORKSHOP OUTLINE
  • PCB Design for cleaning
  • Testing component compatibility
  • Flux compatibility with cleaning solvents
  • Solubility of soldering residues
  • Cost of process chemistry and equipment
  • Inline or batch cleaning options
  • Process cleaning capability, simple shop floor analysis methods
  • Water, semi aqueous or solvent?
  • Simple steps to evaluate machine cleaning capability
  • Determining cleanliness standards
  • Ionic, SIR and visual inspection methods
  • Environmental requirements of cleaning
  • Cleaning no clean flux residues
WHO SHOULD ATTEND

The session is ideally suited with staff facing the daunting task of implementing cleaning processes or assessing the implementation in their supply chain. This session is ideally suited to design, production and quality engineers looking at future technology and maintaining a company technology roadmap. It’s vital to subcontractors to be up-to-date with new technology and its possible implementation along with material and equipment requirements for future customers.

If a delegate has a process example they would like cover in the workshop it will need to be provided in advance of the session with photographs by email to the presenter.

BUILDING RELIABLE PRINTED CIRCUIT BOARDS THE LESSONS LEARNED


7th August 2018


BHANU SOOD

Reliability and Risk Assessment Branch
NASA Goddard Space Flight Center, USA


WORKSHOP OVERVIEW

Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant.

The continuity of the electric path of a signal is critical for the functionality and reliability of PCBs. An open circuit is defined as an electrical discontinuity, and will adversely affect the functionality of the board. This well known failure mode can be induced by multiple influences such as materials, design, equipment, method, use or assembly. The physical processes by which the causes transforms into the observed effect (mechanism) will depend on the life cycle conditions as well as the location (site) on the PCB.

A short circuit will occur whenever a low resistance path is formed between conductors in the presence of a voltage potential. This can sometimes result in catastrophic damage to the PCB or the whole system with fire or explosion in the worst case. This type of defect is also known to cause intermittent failures in electronic devices, which can be tedious to troubleshoot. A short circuit can be the start of a propagating fault that will burn or melt the PCB material leaving no evidence of the root cause. Failure to hold the stacked layers in the out of plane “z” direction will result in a failure mode known as delamination, which is a non- acceptable condition on PCB integrity

This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues.


WORKSHOP OUTLINE
  • Introduction to printed circuit board design consideration
  • PCB types
    • > classified on basis of application, processing, material
  • Current PCB technology
    • > halogen-free, RoHS, demanding application
  • Case study 1
    • > electrical short failure in PCBs, cause and prevention
  • Reliability terminology pertaining to PCBs
  • Common failure modes
  • Review of failure mechanisms
    • > infant mortality failure, overstress or wearout
  • Mechanisms leading to opens
    • > design, materials, test, use conditions
  • Mechanisms leading to shorts
    • > materials, process, moisture, contaminants
  • Mechanisms leading to electrical intermittents
    • > CAF, dendrites, cratering
  • Case study 2
    • > delamination in PCBs, cause and prevention
  • Effects of ambient conditions
  • Mitigation efforts
  • Closure
WHO SHOULD ATTEND

PCB Engineers, Quality Engineers, Design Engineers, Quality Assurance functions and, personnel involved with PCB procurement or quality assurance activities within the company.

PRINTED CIRCUIT BOARD INSPECTION &
QUALITY CONTROL PCB FAILURES CAUSES & CURES


9th August 2018


BOB WILLIS

President & Principal Consultant
Bobwillisonline.com, England


WORKSHOP OVERVIEW

The printed circuit board is the building block of any electronic assembly and as such must exceed specication and be totally compatible with the assembly processes used in modern assembly. Failures in PCB fabrication can be cosmetic, often the most common reason for rejection in manufacture or assembly. Failures can be found during assembly and nal test which are not ideal but much better than field returns.

A common fault is no or incorrect specication of the bare board in design or via purchasing. This can lead to failures in manufacture. Through a better understanding how IPC standards can help engineers make the correct selection and procurements of good quality PCBs

In his presentation Bob will highlight test methods you can try and tricks of the trade to understand how PCBs can fail and how to eliminate many of the common causes. After the workshop there is a Q&A session which provides ample time for all delegate questions to be answered.


WORKSHOP OUTLINE
  • Through hole plating failures
  • CAF contamination shorts
  • PCB Delamination
  • Nickel/Gold - Black pad & Black Tar
  • Inner layer separation
  • Solder mask cracking
  • Outgassing
  • Need for product specifications
  • Auditing a PCB supplier

    Common Defects Experienced in Industry and Covered in the Workshop

    • -Design related defects
    • -Cosmetics – not real defects
    • -Cleanliness
    • -Poor solderability
    • -Nickel/Gold, silver, OSP joint failures
    • -Delamination
    • -Copper plating thickness/leaching
    • -Solder mask alignment
    • -Solder mask lifting/undercutting
    • -Solder balling
    • -Via hole failure
    • -Outgassing
    • -Etch defects
    • -PCB Bow & twist
WHO SHOULD ATTEND

The session is ideally suited to process, quality and design engineers who are very closely involved with bare PCBs. It will also benefit staff involved in inspection and testing printed boards in fabrication or assembly. Assembly technicians are the first people to see the bare boards when they hit the shop floor and their better knowledge of board issues will prevent increased failures during assembly

If a delegate has a process example they would like cover in the workshop it will need to be provided in advance of the session with photographs by email to the presenter.

FAILURE ANALYSIS IN SEMICONDUCTOR PACKAGE ASSEMBLY


9th August 2018


Dr. TAN CHER MING

Principal Consultant, Taiwan.


WORKSHOP OVERVIEW

Quickly finding and eliminating package defects and failures due to assembly issues is critical to the IC business. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of people in many disciplines is needed in order to achieve high yield and reliability. Each needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods. The workshop participants will learn about failure analysis methods and reliability.


WORKSHOP OUTLINE
  • Package background
  • FA in Assembly how is it dierent from board level or system level
  • Why do failure analysis?
  • Is reliability important or part of FA?
  • Incoming wafer FA
  • The Reliability Bath Tub Curve, its origin and implications
  • Mechanical causes of assembly failures
  • Thermal causes of assembly failures
  • Accelerated Testing and Estimation of Useful Operating Life
    • > Burn-in as failure analysis
    • > Temperature cycling methods
    • > Drop testing (to find weak areas in design or assembly)
    • > Shock/vibration tests
  • Methods to detect failures (destructive and non-destructive)
    • >FTIR
    • >Thermal cycling (TCA, TCB, etc.)
    • >FIB, focused ion beam
    • >SEM, scanning electron micrograph
    • >Interference pattern testing for package stress
    • >Thermal imaging
    • >Physical inspection, visual imaging, microscope
    • >De-capping methods
  • FA used to predict mean time to failure, MTTF
  • Revere engineering
  • Summary
  • Mechanical requirements driving package materials
  • Assembly failure mechanisms
    • > Substrate design, warpage and cracks
    • >Underfill process control
    • >Wire bond failures
    • >Flip chip failures
    • >Substrate bake out
WHO SHOULD ATTEND

Production and quality control engineers, Manufacturing supervisors, Manufacturing engineers and technicians, Front of the line packaging engineers and technicians, Operations management, planning and support personnel, Fab quality engineers needing to understand Assembly failure analysis

FLIP CHIP PACKAGE TECHNOLOGY AND ASSEMBLY PROCESSES


8th August 2018


VERN SOLBERG

Principal Consultant,
Solberg Technical Consulting, USA


WORKSHOP OVERVIEW

Flip chip packaging is not new but new technology requires more connections between the die and package, a tighter bump pitch and more functionally in the package. Tablets and smart phones all use flip chip packaging with thinned die and thin packages. All technology drivers bring new issues that must be addressed. These issues include new copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-ow options, new underfill flow materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach lms. Wafer thinning processes and some stacked die package options will be reviewed. This workshop will begin with a discussion of current flip chip assembly. We will then discuss the new technology options and issues

The objective of this workshop is to provide an improved understanding of current ip chip package options and assembly ows. The newer HVM package material and desig n options are discussed. Wafer thinning and handling including bonding and debonding methods will be covered. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.


WORKSHOP OUTLINE
  • review of package designs and market drivers
    • > Major flip chip package types including wafer level package, WLP, multichip packaging, MCP and system on chip, SoC
    • > Single chip and multiple chip package designs
  • Semiconductor roadmaps for Assembly
    • > Smaller packages for mobile applications and larger packages for more functionally
  • Introduction to package assembly processes
    • > HVM flip chip assembly process flows
  • Major classes of bumps including electroplated, solder paste and stud bumps
  • Wafer saw and dicing processes
    • > Laser dicing, plasma dicing and dierent saw blade types
  • Die bond/die attach processes using dierent die attach materials and reflow processes
  • Flip chip solder joint reliability
    • > Failure modes and ways to avoid them
  • Underfill process options including no-flow underfill
    • > Underfill material selection
  • Wafer level packaging processes
  • Embedded passive devices in the substrate
  • Cutting edge package technology including 3D packaging and TSV process options
    • > Technology drivers for 3D packages
    • > Die stacking options in 3D packages including chip to chip and chip to wafer
  • Summary and review
WHO SHOULD ATTEND

Manufacturing engineers and technicians, Process engineers, Assembly integration engineers, Material science engineers, Equipment support technicians, Technical marketing engineers with some technical background.

STATISTICAL PROCESS CONTROL FOR ELECTRONIC ASSEMBLY


9th August 2018


RONALD C. LASKY, PHD, PE, LSSMBB

Instructional Professor, Thayer School of Engineering,
Dartmouth College


WORKSHOP OVERVIEW

Statistical Process Control (SPC) is vital for monitoring and controlling electronic assembly processes, especially stencil printing. This workshop will cover the basics of SPC for stencil printing and teach the student how to establish an SPC program for stencil printing or other SMT process at their facility.

Benefits

Stencil Printing causes about two thirds of end of the line defects. Hence, establishing an SPC Stencil Printing program for electronic assembly will increases first pass yields and improve product reliability.


WORKSHOP OUTLINE
  • Statistics Refresher
    • > Statistical Thinking
      •    - The Case of the Harassing Squirrel
      •    - Your Favorite Sports Team
      •    - Statistical Thinking in Life
    • >Probability Review
      •    -Throwing the Dice
      •    -The Most Dangerous Job in World War II
      •    -In Class Examples
    • > The Normal Distribution
      •    - Why it is so Common
      •    - The Central Limit Theorem
      •    - In Class Examples
    • >Confidence Intervals
      •    - What are Confidence Intervals?
      •    - Why do We Choose 95%?
      •    - The Effect of Sample Siz
      •    - In Class SMT Examples
    • > Hypothesis Testing
      •    - What is Hypothesis Testing?
      •    - How Does Hypothesis Testing Relate to Confidence
        Intervals?
      •    - In Class SMT Examples
    • > Statistical Process Control Introduction
      •    - What is Statistical Process Control (SPC)
      •    - How Does SPC Fit into a Lean Six Sigma Program
      •    - Common Cause Variation with Examples
      •    - Special Case Variation with Examples
    • > Understanding Variation in Processes
      •    - Accuracy and Precision and Their Differences
      •    - Accuracy and Precision Examples
    • >Gage R & R Analysis
      •    - What is Gage R & R Analysis?
      •    - Gage R & R Examples with Minitab
      •    - Gage R & R Analysis Measures Precision
  • What about Accuracy?
    • > Shewhart’s Rules
      •    - Who was Shewhart?
      •    - Why did He Create His Rules?
      •    - What are the Eight Rules
      •    - The Derivation of Several of the Rules
      •    - Variables Data
      •    - The X Bar – R Chart
      •    - In Class SMT Examples
  • Calculating the Control Limits by Hand
    • >Examples in SMT Assembly with Minitab
    • >Attribute Data
    • >The C Chart
    • >Cp and Cpk
  • Cp an Cpk: Where the Specs and Process Capability Face Off
  • The Importance of the Data Being Normal
  • Calculating Cp and Cpk with in Class Examples Cpk and Ppk
  • In Class Examples using Minitab
  • Can You Average Cps and Cpks?
  • “Cheating” Examples with Cp and Cpk
  • Cp and Cpk for Non-Linear Data and Caveats
  • Confidence Intervals for Cpk
  • Hypothesis Testing of Cpk
WHO SHOULD ATTEND

This course is designed for managers, engineers, executives, supervisors, or anyone who wish to have in depth understanding on the application SPC methodology for process and quality optimization

WAFER LEVEL FAN OUT IN ADVANCED
PACKAGING ASSEMBLY AND TECHNOLOGY


9th August 2018


VERN SOLBERG

Consultant in SMT and microelectronics
design and manufacturing technology


WORKSHOP OVERVIEW

This workshop provides details on current and future assembly processes and technologies used in fan out package assembly. Examples taken from mobile smart phones to advanced server computing will be presented.

Currently there are several choices for package assembly using fan out wafer level packages (FOWLPs). The original fan-out package; the embedded wafer-level ball-grid array (eWLB) continues to be popular. At the low cost end are low density fan out packages with <500 IOs with >8 micron L/S. At the high cost end are stacked die packages with >500 Ios and < 8 micron L/S. Multiple die can now be included in a fan out package incorporating stacked die connected using Through Silicon Vias (TSVs).

The fan out chip scale package, FOCSP, will be used as current state of the art example in the workshop. The package end user, designer and sub-cons must compare all package options on the basis of functional attributes including form factor, I/O density, performance & cost to select appropriate package from the many fan out options available

The transition from the use of a 200 or 300mm wafer carrier to a panel as the assembly vehicle will be discussed. The workshop begins with a detailed comparison of advanced packaging technologies including all varieties of fan out packages including FOWLPs & SiPs to 3D stacked dice interconnected with TSVs. The workshop will discuss a chip first and chip last assembly option for fan out packages. Both wire bond and flip chip options will be compared. Types of fan out packaging include Wafer Level Fan Out, Panel Level Fan Out with embedded die, and Chip Last Fan Out packaging. These package options with low cost materials and process flows create simple low density devices

The workshop continues with packaging assembly ows for each major package type. Details on copper pillar flip chip interconnect structures, process ows and materials will be discussed. Copper pillar flip chip attachment methods including thermal reow, thermo-compression bonding and the use of non-conductive paste will be reviewed. The objective of this workshop is to provide the delegates with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes.


WORKSHOP OUTLINE
  • Semiconductor Roadmap for Assembly
  • Fan out wafer level packaging options
  • Thermal requirements driving package material
  • Mechanical requirements driving package materials
  • Wafer Thinning Processes and Handling
  • The use of a carrier and temporary bonding materials
  • Coreless substrate vs. cored substrate assembly
  • Wafer carriers or switch to panels?
  • Wafer dicing methods including laser scribing, saw, and plasma
  • Wirebonded stacked die
  • Flipchip package options
  • FOWLP options
  • FOCSP options
  • Wire bond assembly
  • Die attach material selection
  • Gold, aluminum or copper wire assembly dierences
  • Stacked die wire bonding assembly process flow
  • Silicon interposer design and uses in 2.5D packages
  • Stacked die packages using TSV
  • Thermal control in 3D packages
  • Bump material options
  • Solder paste, electroless plating bump materials,non-lead solders, copper pillars
  • Bump reflow processes
  • Thermal reflow and thermal compression bonding
  • Package material selection to meet end user requirements
  • Summary and review
WHO SHOULD ATTEND

Manufacturing engineers and technicians, Manufacturing supervisors, Production and quality control engineers, Front of the line packaging engineers and technicians, Operations management, planning and support personnel

IMPROVING MANUFACTURING PRODUCTIVITY AND
RELIABILITY THROUGH OPTIMUM ASSEMBLY PROCESSES


7th & 8th August 2018


PHIL ZARROW

President & Principal Consultant
ITM Consulting, USA


WORKSHOP OVERVIEW

This workshop drives awareness and solutions to the adverse impact that nonoptimal assembly practices and processes have on the product quality and financial success of electronic assembly businesses. A comprehensive perspective on problem issues is developed for the most currently critical electronic assembly process, materials (both existing and emerging), equipment, procedures, and methods. Most importantly, practical solutions are presented. Key issues that consistently result in assembly problems and low yields are identied and resolved. This workshop is intended for anyone involved in directing, developing, managing and/or executing assembly line operations including managers, line supervisors and line engineers involved in manufacturing, design and quality engineering.


WORKSHOP OUTLINE
  • Introduction
  • Optimization Objective
    • > Getting the most productivity from an existing line
    • > Definition of “Best Practices”
  • Process Characterization
  • Design for Manufacturability
  • Best Practices in the Assembly Process
    • > Solder Paste Printing process best practices
  • Solder Paste Eval
  • Optimizing Printing Process
    • > Pick and Place best practices
  • Pick and Place categorization
  • Feeder considerations
  • Understanding through-put and cycle times - De-rating factors
  • Optimizing Set-up
  • Optimizing the placement process
    • > Reflow soldering best practices
  • Convections Dominant
  • Vapor Phase
  • Vacuum Reflow
  • Reflow Requirements and Specification
  • Optimizing the Reflow process
    • > Through-hole soldering considerations and best practices
  • Wave Soldering
    • > Selective soldering methodologies, equipment and best practices
    • > Intrusive reflow soldering of through-hole components
  • Cleaning vs No-Clean considerations and best practices
  • Best Practices concerning “challenging technologies”
    • > QFNs
    • > Ultra-miniature components (0201s, 01005s,ultra-fine pitch BGAs and CSPs
  • Reflow methodologies
WHO SHOULD ATTEND

This course is intended for Manufacturing, Process, Design, Test and Quality Engineering personnel as well as Management who are involved in the production of surface mount or mixed technology assemblies

PRACTICAL DESIGN OF EXPERIMENTS (DOE)
FOR PROCESS AND QUALITY OPTIMIZATION


8th & 9th August 2018


BONG KOK LIANG

Principal Consultant


WORKSHOP OVERVIEW

Design of Experiments (DOE) is an off-line quality improvement methodology that dramatically improves industrial products and processes thus enhancing productivity and reducing costs. Input factors are varied in a planned manner to efciently optimize output responses of interest with minimal variability

This course will provide delegates with basic DOE knowledge & techniques that have been specically designed to deal with common process optimization problems that encountered by engineers in industry. These techniques will be demonstrated by using Minitab software with actual industrial data.

Learn how to:

  • explain the fundamental principles of designed experiments
  • generate and analyze full factorial, fractional factorial, screening designs and Response Surface Design (RSM)
  • interpretation of analysis results and identify areas for improvement
  • Training Approach
    This practical course combines classroom teaching, practical exercises, and group discussion with actual factory based projects to provide a complete action learning experience. The course has been designed to enable all participants leave the training room with a set of new knowledge, tools, skills and direct experience of how to use DOE methodology to perform process and quality improvement in a real company setting.

    Prerequisite: Some knowledge on basic statistics and application of Minitab software

    Training facilities: computer installed with Minitab software (version 16 and above). Download 30 days fully functional Minitab software from (www.minitab.com). Minitab is a powerful statistical data analysis software which is widely used in industry.


    WORKSHOP OUTLINE

      DAY ONE

      Section 1 : Introduction to Design of Experiment (DOE)

    • What is DOE?
    • DOE vs. One-Variable-At-A-Time
    • The dierent stages of quality improvement
    • Types of experiment
    • The challenges faced by engineers
    • Steps for DOE
    • Practical examples


    • Section 2 : Full Factorial design and response optimization

    • Factors vs response
    • Completely randomized design
    • Techniques to create factorial design
    • Coded setting and orthogonal design
    • Replicating & blocking the design
    • Tree diagram
    • Meaning of Main Eects and Interactions
    • DOE modeling
    • Un-coding the setting
    • Cube plot
    • Setup of Response optimizer & optimization plot
    • Interpretation of results and identify necessary improvement actions
    • Practical application exercise by using Minitab software

      DAY TWO

      Section 3 : Screening Design

    • Fractional vs full factorial design
    • Confounding eect
    • Design resolution
    • Center points, & residual plots
    • Prediction profiler
    • Desirability function
    • Practical application exercise by using Minitab software


    • Section 4 : Response Surface Methodology (RSM)

    • Basic concepts of RSM
    • Application of RSM
    • Central composite design
    • Box-Behnken design
    • Contour profiler with high low limits
    • Response surface plot analysis
    • Response optimization
    • Interpretation of results and identify necessary improvement actions
    • Practical application exercise by using Minitab software
    WHO SHOULD ATTEND

    This course is designed for managers, engineers, executives, supervisors, or anyone who wish to have in depth understanding on the application DOE methodology for process and quality optimization.